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FEATURES 155 Mbps Clock Recovery and Data Retiming Permits CCITT G.958 Type A Jitter Tolerance Permits CCITT G.958 Type B Jitter Transfer Random Jitter: 0.6 rms Pattern Jitter: Virtually Eliminated Jitter Peaking: Fundamentally None Acquisition: 30 Bit Periods Accepts NRZ Data without Preamble Single Supply Operation: -5.2 V or +5 V 10 KH ECL Compatible
DATA INPUT VOLTAGE CONTROLLED PHASE SHIFTER
Data Retiming Phase-Locked Loop AD805*
CLOCK RECOVERY AND DATA RETIMING APPLICATION
PHASE DETECTOR
LOOP FILTER
GAIN
OBS
PRODUCT DESCRIPTION
RETIMING MODULE
VCXO (EXTERNAL) RECOVERED CLOCK
AD805
The AD805 is a data retiming phase-locked loop designed for use with a Voltage-Controlled Crystal Oscillator (VCXO) to perform clock recovery and data retiming on Nonreturn to Zero (NRZ) data. The circuit provides clock recovery and data retiming on standard telecommunications STS-3 or STM-1 data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit is used with the AD805 for specification purposes. Similar circuit performance can be obtained using other commercially available VCXO circuits. The AD805-VCXO circuit used for clock recovery and data retiming can also be used for large factor frequency multiplication.
The AD805-VCXO circuit meets or exceeds CCITT G.958 regenerator specifications for STM-I Type A jitter tolerance and STM-1 Type B jitter transfer. The simultaneous Type A, wideband jitter tolerance and Type B, narrow-band jitter transfer allows the use of the AD805-VCXO circuit in a regenerative application to overcome optical line system interworking limitations based on signal retiming using Type A passive tuned device technology such as Surface-Acoustic-Wave (SAW) or dielectric resonator filters, with Type B active devices such as Phase-Locked Loops (PLLs). The circuit VCXO provides a stable and accurate clock frequency signal with or without input data. The AD805 works with the VCXO to dynamically adjust the recovered clock frequency to the frequency associated with the input data. This frequency control loop tracks any low frequency component of jitter on the input data. Since the circuit uses the VCXO for clock recovery, it has a high Q for excellent wideband jitter attenuation. The jitter transfer characteristic of the circuit is within the jitter transfer requirements for a CCITT G.958 STM-1 Type B regenerator, which has a corner frequency of 30 kHz. The AD805 overcomes the higher frequency jitter tolerance limitations associated with traditional high Q, PLL based clock and data recovery circuits through the use of its data retiming loop. This loop, made up of the AD805's voltage-controlled
*Protected by U.S. Patent No. 5,036,298
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RETIMED DATA
phase shifter, phase detector, and loop filter, act to align input data phase errors to the stable recovered clock provided by the VCXO. The range of the voltage-controlled phase shifter, at least 2 Unit Intervals (UI), and the bandwidth of this loop, at roughly 3 MHz, provide the circuit with its wideband jitter tolerance characteristic. The circuit can acquire lock to input data very quickly, within 44 bit periods, due to the accuracy of the VCXO and the action of the data retiming loop. Typical integrated second-order PLLs take at least several thousand bit periods to acquire lock. This is due to their having a wide tuning range VCO. Decreasing the loop damping of a traditional second-order PLL shortens the length of the circuit's acquisition time, but at the expense of greater jitter peaking. The AD805-VCXO circuit is a second- order PLL that has no jitter peaking. The zero used to stabilize the control loop of the traditional second-order PLL effects the closed-loop transfer function, causing jitter peaking in the jitter transfer function. In the AD805-VCXO circuit, the zero needed to stabilize the loop is implemented in the feedback path, in the voltage-controlled phase shifter. Placing the zero in the feedback path results in fundamentally no jitter peaking since the zero is absent from the closed-loop transfer function. Output jitter, determined primarily by the VCXO, is a very low 0.6 rms. Jitter due to variations in input data density, pattern jitter, is virtually eliminated in the circuit due to the AD805's patented phase detector. The data retiming loop of the AD805 can be used with a passive tuned circuit (155.52 MHz) such as a bandpass or a SAW filter for clock recovery and data retiming. The data retiming loop acts to servo the phase of the input data to the phase of the recovered clock from the passive tuned circuit in this type of application (see APPLICATIONS). The AD805 uses 10 KH ECL levels and consumes 375 mW from a +5 V or a -5.2 V supply. The device is specified for operation over the industrial temperature range of -40C to +85C and is available in a 20-pin plastic DIP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AD805-SPECIFICATIONS (V
Parameter NOMINAL DATA RATE
1
EE
= VMIN to VMAX, TA = TMIN to TMAX ( unless otherwise noted)
Min 50 AD805BN Typ Max 155.52 70 7 7 0.6 0.6 375 125 12.5 2.2 2.2 0.84 0.65 440 147 16 3.2 3.0 1.4 0.85 0 10 0.12 1.1 44 33 33 1.0 1.0 Units Mbps ppm of Nominal Data Rate Degrees Degrees Degrees rms Degrees rms Unit Intervals p-p Unit Intervals p-p Unit Intervals p-p Unit Intervals p-p Unit Intervals p-p Unit Intervals p-p Unit Intervals p-p dB kHz ns Bit Periods Bit Periods Volts Volts
Condition
TRACKING RANGE/CAPTURE RANGE 1 STATIC PHASE ERROR 1 OUTPUT JITTER1 JITTER TOLERANCE1 27-1 PRN Sequence 223-1 PRN Sequence 27-1 PRN Sequence 223-1 PRN Sequence f = 10 Hz f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz f = 650 kHz f = 1.3 MHz 27-1 PRN Sequence
OBS
JITTER TRANSFER1 Peaking Bandwidth RECOVERED CLOCK SKEW ACQUISITION TIME TRANSITIONLESS DATA RUN
1
VCXO CONTROL OUTPUT RESISTANCE VCXO Control Voltage High Level (V CC - VOH) VCXO Control Voltage Low Level (V OL - VEE)
POWER SUPPLY Voltage (VMIN to VMAX) Current
INPUT VOLTAGE LEVELS Input Logic High, V IH Input Logic Low, VIL OUTPUT VOLTAGE LEVELS Output Logic High, VOH Output Logic Low, V OL INPUT CURRENT LEVELS Input Logic High, IIH Input Logic Low, IIL OUTPUT SLEW TIMES Rise Time (tR) Fall Time (tF) BUFFERED CLOCK DISTORTION (DUTY CYCLE DISTORTION) Recovered Clock Output OPERATING TEMPERATURE RANGE (TMIN to TMAX)
1
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TRCS 0.2 0.6 30 1000 500 27-1 PRN Sequence No Load No Load 1000 1 0.8 1.3 1.15 -4.5 TA = +25C, VEE = -5.2 V -5.2 70 -5.5 90 95 TA = +25C -1.08 -1.95 -1.08 -1.95 TA = +25C 125 80 TA = +25C 20%-80% 80%-20% = 1/2, TA = +25C, VEE = -5.2 V -40 0.75 0.75 1.5 1.5 TA = +25C 0.5 +85 Condition Min -4 50 100 70 500 Typ 155.52 -1 Max
-0.72 -1.59 -0.72 -1.60
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Volts mA mA Volts Volts Volts Volts A A ns ns % C Units MHz Volts ppm of Center Frequency kHz N/A
VCXO CIRCUIT SPECIFICATIONS
Parameter CENTER FREQUENCY CONTROL VOLTAGE VCXO TUNING RANGE MODULATION BANDWIDTH TRANSFER FUNCTION
Positive, Monotonic
NOTES 1 These specifications reflect the performance of the circuit shown in Figure 12. VCXO circuit parameters critical to overall circuit performance are listed above. 2 This specification results from tests accurate to 0.1 dB, and from statistical analysis of the test results distribution. The AD805-VCXO circuit has no jitter peaking. Reference the discussion in the THEORY OF OPERATION section. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6 V Input Voltage (Pin 19 or 20 to VEE) . . . . . . . . VEE to +300 mV Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . +300C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of the specification is not implied. Exposure to an absolute maximum rating condition for an extended period may adversely affect device reliability.
DATAOUT 50%
CLKOUT 50%
TRCS
Figure 1. Recovered Clock Skew (See Specifications Page)
PIN DESCRIPTIONS
Number Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DATAOUT DATAOUT VCC2 CLKOUT CLKOUT SUBST VEE VCC1 AVEE ASUBST NC VCXO CONTROL AVCC VCC1 VEE CLKIN CLKIN SUBST DATAIN DATAIN Description Differential Retimed Data Output Differential Retimed Data Output Digital Ground Differential Recovered Clock Output Differential Recovered Clock Output Substrate Digital VEE Digital Ground Analog VEE Analog Substrate No Connection VCXO Control Voltage Output Analog Ground Digital Ground Digital VEE Differential Clock Input Differential Clock Input Substrate Differential Data Input Differential Data Input
OBS
PIN CONFIGURATION
DATAOUT DATAOUT VCC2 1 2 3 4 5 20 DATAIN DATAIN SUBST 19 18 17 16 CLKOUT CLKIN CLKOUT SUBST
AD805
CLKIN VEE
6 7 8
TOP VIEW (Not to Scale)
15
NOTES: PIN 6 AND 18 ARE DIGITAL SUBSTRATE AND SHOULD BE CONNECTED TO PINS 7 AND 15 WHICH ARE DIGITAL VEE .
VEE
14 13 12
VCC1
PIN 10 IS ANALOG SUBSTRATE AND SHOULD BE CONNECTED TO PIN 9, WHICH IS ANALOG VEE.
VCC1 AVEE ASUBST
AVCC VCXO CONTROL NC
9 10
11
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Operating Temperature -40C to +85C
JA
NC = NO CONNECT
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WARNING!
ORDERING GUIDE AND THERMAL CHARACTERISTICS
Device AD805BN
Description 20-Pin Plastic DIP
Package Option N-20
80C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD805 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
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AD805
GLOSSARY Jitter Tolerance
AD805 performance is specified using a Vectron C0-434Y ECL Series Hybrid VCXO, SCD No. 434Y2365.
Nominal Data Rate
This is the data rate that the circuit is specified to operate on. The data format is Nonreturn to Zero (NRZ).
Operating Temperature Range (T MIN to TMAX)
Jitter tolerance is a measure of the circuit's ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation and is usually specified in Unit Intervals (UI). The circuit will have a bit error rate less than 1 x 10-10 when in lock and retiming input data that has the specified jitter applied to it. Refer to the THEORY OF OPERATION section for a description of the jitter tolerance of the AD805-VCXO circuit.
Jitter Transfer
OBS
Tracking Range Capture Range Static Phase Error Recovered Clock Skew, T RCS Data Transition Density, Transitionless Data Run Jitter
This is the operating temperature range of the AD805 in the circuit. Each of the additional components of the circuit is held at 25C, nominal. The operating temperature range of the circuit can be extended to the operating temperature range of the AD805 through the selection of circuit components that operate from TMIN to TMAX. This is the range of input data rates over which the circuit will remain in lock. The VCXO CONTROL voltage range and the VCXO frequency range determine circuit tracking range. This is the range of frequencies over which the circuit can acquire lock. The VCXO CONTROL voltage range and the VCXO frequency range determine circuit capture range.
The circuit exhibits a low-pass filter response to jitter applied to its input data. The circuit jitter transfer characteristics are measured using the method described in CCITT Recommendation G.958, Geneva 1990, Section 6.3.2. This method involves applying sinusoidal input jitter up to the jitter tolerance mask level for an STM-1 Type A regenerator.
Bandwidth
This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error and IC input and output signals prohibit direct measurement of static phase error. This is the time difference, in ns, between the recovered clock signal rising edge midpoint and midpoint of the rising or falling edge of the output data signal. Refer to Figure 1. This is a measure of the number of data transitions, from "0" to "1" and from "1" to "0," over many clock periods. is the ratio (0 1) of data transitions to clock periods.
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Peaking Acquisition Time Buffered Clock Distortion
This describes the frequency at which the circuit attenuates sinusoidal input jitter by 3 dB. This describes the maximum jitter gain of the circuit in dB. This is the transient time, measured in bit periods, required for the circuit to lock on input data from its free-running state. This is a measure of the duty cycle distortion at the AD805 CLKOUT signals relative to the duty cycle distortion at the AD805 CLKIN signals.
Bit Error Rate vs. Signal-to-Noise Ratio
The AD805 is intended to operate with standard ECL signal levels at the data input. Although not recommended, smaller input signals are tolerable. Figure 6 shows the bit error rate performance versus input signal-to-noise ratio for input signal amplitudes of full 900 mV ECL, and decreased amplitudes of 80 mV and 20 mV. Wideband amplitude noise is summed with the data signals as shown in Figure 2. The full ECL, 80 mV, and 20 mV input signals give virtually indistinguishable results.
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This is measured by interrupting an input data pattern with = 1/2 with a block of data bits without transitions, and then reapplying the = 1/2 input data. The circuit will handle this sequence without making a bit error. The length of the block of input data without transitions that an AD805-VCXO circuit can handle is a function of the VCXO K0. The VCXO in the circuit of Figure 12 has a K0 of 60 radians/volt, nominally. This is the dynamic displacement of digital signals from their long term average positions, measured in degrees rms, or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock. Jitter on the recovered clock causes jitter on the retimed data.
Output Jitter
The axes used for Figure 6 are scaled so that the theoretical Bit Error Rate vs. Signal to Noise Ratio curve appears as a straight line. The curve that fits the actual data points has a slope that matches the slope of the theoretical curve for all but the higher values of signal-to-noise ratio and lower values of bit error rate. For high values of signal-to-noise ratio, the noise generator used clips, and therefore is not true Gaussian. The extreme peaks of the noise cause bit errors for high signal to noise ratios and low bit error rates. The clipping of the noise waveform limits bit errors in these cases.
This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudo-random input data sequence (PRN Sequence). The random output jitter of the VCXO contributes to Output Jitter.
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AD805
+
DIFFERENTIAL SIGNAL SOURCE POWER COMBINER
+
0.47F 50
DATAIN 100 CIRCUIT UNDER TEST DATAIN POWER COMBINER 75 POWER SPLITTER GND 1.0F 180
-
0.47F
JITTER TOLERANCE - UIp-p
+
50
10
-5.2 V
1 CCITT TYPE A MASK
OBS
NOISE SOURCE
0 -5
FILTER
0.1 0.1
1
10 FREQUENCY - kHz
100
1000
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test: Block Diagram
0.3 UI INPUT JITTER
JITTER GAIN - dB
BIT ERROR RATE
TYPE A MASK INPUT JITTER -10 1.3 UI INPUT JITTER -15
CCITT TYPE B MASK
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E-1
5E-2 3E-2 2E-2
Figure 5. Jitter Tolerance
E-2
5E-3 3E-3 2E-3
80mV
3 4
5E-4 3E-4 2E-4
5 6
ECL
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20mV
IOUT
-20 1 10 100 JITTER FREQUENCY - kHz 1000
8 10 12 E-15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S/N - dB
Figure 3. Jitter Transfer - Bandwidth
Figure 6. Bit Error Rate vs. Signal-to-Noise Ratio
0.3 UI INPUT JITTER -1
V CC
VCXO CONTROL VOLTAGE - Volts
2.0 AD805 1.5
JITTER GAIN - dB
1.3 UI INPUT JITTER
V EE = -5.2V
VCC - VOH 1.0
-3 CCITT TYPE A MASK INPUT JITTER
0.5 VOL - VEE 0
-5 1 JITTER FREQUENCY - kHz 10
-200
0 IOUT - A
200
400
Figure 4. Jitter Transfer - Peaking
Figure 7. VCXO Control Voltage vs. Load
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AD805
THEORY OF OPERATION
The AD805 is a delay- and phase- locked loop circuit for clock recovery and data retiming from an NRZ-encoded data stream. Figure 8 is a block diagram of the device shown with an external VCXO. The AD805-VCXO circuit tracks the phase of the input data using two feedback loops that share a common control voltage. A high speed delay-locked loop path uses an on-chip voltage-controlled phase shifter (VCPS) to track the high frequency components of jitter on the input data. A separate frequency control loop, using the external VCXO, tracks the low frequency components of jitter on the input data.
AD805
VOLTAGE CONTROLLED PHASE SHIFTER PHASE DETECTOR LOOP FILTER INTERNAL LOOP CONTROL VOLTAGE
peaking in any regenerative stage can contribute to hazardous jitter accumulation.
ORDINARY PLL JITTER OUT (dB) JITTER IN 0 dB Y(s) X(s)
Z(s) X(s)
AD805 - VCXO
1
sLOW
sHIGH
LOG
OBS
RETIMING MODULE VCXO (EXTERNAL) RECOVERED CLOCK RETIMED DATA
DATA INPUT
Figure 10. Circuit Jitter Transfer Functions
VCXO CONTROL VOLTAGE
Figure 8. AD805-VCXO Clock Recovery Block Diagram
The two loops work together to null out phase error. For example, when the clock is behind the data, the phase detector drives the VCXO to a higher frequency and also increases the delay through the VCPS. These actions serve to reduce the phase error. The faster clock picks up phase while the delayed data loses phase. When considering a static phase error, it is easy to see that since the control voltage is developed by a loop integrator, the phase error will eventually reduce to zero.
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100
JITTER TOLERANCE - UIp-p
The error transfer function, e(s)/X(s), has the same high pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wide-band jitter accommodation since the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. The circuit has an error transfer bandwidth of 3 MHz and a jitter transfer bandwidth of 10 kHz. The circuit's two loops contribute to overall jitter accommodation. At low frequencies, the integrator provides high gain so that large jitter amplitudes can be tracked with small phase errors between inputs of the phase detector. In this case, the VCXO is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the VCXO tuning range. A wider tuning range corresponds to increased accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors, so the VCPS remains close to the center of its range, contributing little to jitter accommodation.
Another view of the circuit is that the AD805 VCPS implements the zero that is required to stabilize a second order phase-locked loop and that the zero is placed in the feedback path so it does not appear in the closed-loop transfer function. Jitter peaking in an ordinary second order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Since the AD805-VCXO circuit is free of any zero in its closed-loop transfer function, the circuit is free of jitter peaking. A linearized block diagram of the AD805-VCXO circuit is shown in Figure 9. The two loops simultaneously provide wideband jitter accommodation and narrow-band jitter filtering.
Y
At medium jitter frequencies, the gain and tuning range of the VCXO are not enough to track input jitter. In this case the VCXO control voltage input starts to hit the rails of its maximum voltage swing and the VCXO frequency output spends most of the time at one or the other extreme of its tuning range. The size of the VCXO tuning range therefore has a small effect on the jitter accommodation. The AD805 internal loop control voltage is now larger, so the VCPS takes on the burden of tracking input jitter. The VCPS range (in UI) is seen as the plateau on the jitter tolerance curve (Figure 11). The VCPS has a minimum range of 2 UI.
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AD805-VCXO JITTER TOLERANCE
e X PHASE SHIFTER
+
-
+
K
-
PHASE DETECTOR Z(s) 1 = X(s) s2 + s + 1 K
1 s INT
1 s VCO
Z
10
e(s) s2 = X(s) s2+ Ks + K
1 CCITT TYPE A MASK
Figure 9. AD805-VCXO Circuit Linearized Block Diagram
The jitter transfer function, Z(s)/X(s), is second order and low pass, providing excellent filtering. Note that the jitter transfer function has no zero, unlike ordinary second-order phase-locked loops. This means that the circuit has fundamentally no jitter peaking (see Figure 10). Having no jitter peaking makes this circuit ideal for signal regeneration applications where jitter -6-
0.1 0.1 1 10 100 FREQUENCY - kHz 1000 10000
Figure 11. Jitter Accommodation Design Limit
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The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences between the phase detector inputs are needed to make the internal loop control voltage big enough to tune the range of the VCPS. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the loop integrator determines the jitter accommodation. Since the gain of the loop integrator declines linearly with frequency, jitter accommodation decreases with increasing jitter frequency. At the highest frequencies, the loop gain is very small and little tuning of the VCPS can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error and the residual loop jitter. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the 3 MHz closed-loop bandwidth of the AD805's internal delay-locked loop.
USING THE AD805 Ground Planes APPLICATIONS 155.52 MBPS CLOCK RECOVERY AND DATA RETIMING USING AT&T 157-TYPE VHF VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR
The AD805 design can be used with any VCXO circuit that has a gain of roughly 1 106 rad/volt-sec, a frequency pull range of at least 50 ppm, a positive slope (a greater VCXO control voltage corresponds to a greater output frequency) and a modulation bandwidth of 500 kHz. These VCXO parameters contribute to overall circuit low frequency jitter tolerance and jitter transfer. The output jitter of the overall circuit is largely determined by the output jitter of the VCXO. The AD805 adds little jitter since it just buffers the VCXO frequency output, adding distortion (duty cycle distortion) of only 0.5%. Overall circuit jitter bandwidth is determined by the slope of the VCXO output frequency vs. control voltage curve. A greater slope corresponds to a greater jitter bandwidth. Figure 12 shows a schematic of the AD805 in a 155.52 Mbps clock recovery and data retiming application with an AT&T 157-Type VCXO (see insert). Figures 15 and 16 show typical jitter tolerance and jitter transfer curves for the circuit.
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Power Supply Connections Transmission Lines Terminations Input Buffer
Use of two ground planes, an analog ground plane and a digital ground plane, is recommended. This will isolate noise that may be on the digital ground plane from the analog ground plane.
Power supply decoupling should take place as close to the IC as possible. This will keep noise that may be on a power supply from affecting circuit performance. Use of a 10 F tantalum capacitor between VEE and ground is recommended.
Use of 0.1 F ceramic capacitors between IC power supply or substrate pins and either analog or digital ground is recommended. Refer to schematic, Figure 12, for advised connections. The ceramic capacitors should be placed as close to the IC pins as possible. Connections from VEE to load resistors for DATAIN, DATAOUT, CLKIN, and CLKOUT signals should be individual, not daisy chained. This will avoid crosstalk on these signals. Use of 50 transmission lines are recommended for DATAIN, DATAOUT, CLKIN, and CLKOUT signals. Termination resistors should be used for DATAIN, CLKIN, DATAOUT, and CLKOUT signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the DATAIN and CLKIN signals should be placed as close as possible to the DATAIN and CLKIN pins. Use of an input buffer, such as a 10H116 Line Receiver IC, is suggested for an application where the DATAIN signals do not come directly from an ECL gate, or where noise immunity on the DATAIN signals is an issue.
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Note that the 157-Type VCXO control voltage bandwidth (modulation bandwidth) varies with respect to control voltage from 80 kHz to 500 kHz. The low value of this modulation bandwidth causes some jitter peaking when used with the AD805. The limited modulation bandwidth introduces excess phase in the frequency control loop through the VCXO. This causes the frequency control loop to become less damped. Jitter peaking of 1 dB or 2 dB results in the jitter transfer function. The compensation network on the VCXO control voltage between the AD805 and the 157-Type VCXO shown in Figure 12, effectively reduces the high frequency loop gain through the frequency control loop. The addition of this compensation network eliminates jitter peaking. The compensation network 1 k resistor works with the AD805 VCXO CONTROL 1 k output impedance to halve the loop crossover frequency. This avoids excess phase caused by the limited modulation bandwidth of the 157-Type VCXO.
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-5.2V C9 0.1F R15 130 R16 130 1 2 -5.2V J1 DATAOUT J2 DATAOUT -5.2V C4 0.1F R12 154 R11 154 R6 100 R1 100 R2 100 C3 0.1F C7 0.1F R13 80.6 R14 80.6 3 4 R10 154 R5 100 R9 154 5 6 7 8 -5.2V -5.2V 0.1F -5.2V R17 80.6 C12 0.1F R21 130 9 10 VECTRON CO-434V VCXO 16 8 -5.2V C16 0.1F R18 80.6 C10 Z2 10H116 16 15 14 13 12 11 10 J6 9 DATAIN R19 130 R20 130 J5 DATAIN C11 0.1F -5.2V
1 DATAOUT 2 DATAOUT 3 VCC2 4 CLKOUT R7 100 5 CLKOUT 6 SUBST 7 VEE
DATAIN 20 DATAIN 19 SUBST 18 CLKIN 17 CLKIN 16 VEE 15 VCC1 14 AVCC 13 VCXO CONTROL 12 C8
J3 CLOCKOUT CLOCKOUT
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J4 R4 100 R8 100 R3 100 C5 0.1F 8 VCC1 -5.2V 9 AVEE -5.2V C2 10F C6 0.1F DIGITAL GROUND ANALOG GROUND
-5.2V 0.1F R23 80.6
R22 130
10 ASUBST
NC = NO CONNECT * A NOTCH FILTER MAY BE USED TO FILTER A VCXO CIRCUIT'S SPURIOUS RESPONSE EFFECTIVELY.
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Z1 NC 11 R24 80.6
AD805
6
20mh
OPTIONAL NOTCH FILTER*
ABC
1nF
A
R25 1k
-5.2V
C1 1.0F
C13 0.1F
C B
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1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Z3 AT&T 157-TYPE VCXO 157 AT&T TYPE VCXO CIRCUIT
Figure 12. Evaluation Board Schematic, Negative Supply
Figure 13. Evaluation Board, Component Side
Figure 14. Evaluation Board, Solder Side
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Table I. Evaluation Board, Negative Supply: Components List 155.52 MBPS CLOCK RECOVERY AND DATA RETIMING USING A SURFACE ACOUSTIC WAVE (SAW) FILTER
Reference Designator R1-8 R9-12 R13, 14, 17, 18, 23, 24 R15, 16, 19-22 C2 C3-12, C15 Z1 Z2 Z3
Description Resistor, 100 , 1% Resistor, 154 , 1% Resistor, 80.6 , 1% Resistor, 130 , 1% 10 F, Tantalum 0.1 F, Ceramic Chip AD805 10H116, ECL Line Receiver Vectron CO-434Y VCXO AT&T 157-Type VCXO
Quantity 8 4 6 6 1 11 1 1 1 1
JITTER TOLERANCE - UIp-p
OBS
100 10 AT&T 1 0.1 0.1 1 0 -5
The AD805 can be used with a 155.52 MHz SAW filter circuit for clock recovery and data retiming. In this type of application (refer to Figure 17), the SAW filter circuit is used to generate a 155.52 MHz clock from the input data. The AD805 data retiming loop formed by the voltage-controlled phase shifter, the phase detector and the loop filter, act to servo the phase of the input data to the phase of the recovered clock. The AD805 can compensate up to 180 phase variance through the SAW filter circuit. The AD805 replaces the D Flip-Flop and phase shifter components found in traditional SAW filter-based clock recovery and data retiming circuits. Use of the AD805 eliminates the phase shifter to SAW filter matching needed to get traditional SAW filter-based circuits to perform over operating conditions. The jitter bandwidth and the output jitter of the overall circuit is determined largely by the SAW filter used. The AD805 retimes the input data to the recovered clock and buffers the recovered clock from the SAW filter circuit. The AD805 plays a role in the jitter accommodation of the overall circuit. The AD805's phase shifter range and the bandwidth of the data retiming loop provide for at least 2 UI p-p jitter tolerance to 1 MHz. The length of a transitionless block of data that will not cause the circuit to lose lock or start making bit errors is determined by the Q of the SAW filter used. Figure 17 shows a schematic of the AD805 used with a Toyocom TQS-610J-6R SAW filter. The circuit that precedes the SAW filter feeds the filter with a pulse at each data transition. The line receiver circuit that immediately follows the SAW filter provides gain to the SAW filter output to drive the AD805 CLKIN signals.
VECTRON
CCITT TYPE A MASK
OLE
1000 1000
10 100 JITTER FREQUENCY - kHz
TE
Figure 15. AD805-VCXO Circuit Jitter Tolerance
JITTER GAIN - dB
AT&T 1.3 UI INPUT JITTER -10 CCITT TYPE B MASK
VECTRON 1.3 UI INPUT JITTER -15
-20 1 10 100 JITTER FREQUENCY - kHz
Figure 16. AD805-VCXO Circuit Jitter Transfer
REV. 0
-9-
AD805
-5.2V C9 0.1F R15 130 R16 130 1 2 -5.2V J1 DATAOUT J2 DATAOUT -5.2V C4 0.1F J3 CLOCKOUT J4 CLOCKOUT R4 100 R8 100 R3 100 R7 100 R12 154 R11 154 R6 100 1 DATAOUT 2 DATAOUT 3 V CC2 4 CLKOUT 5 CLKOUT 6 SUBST 7 V EE C5 0.1 8 V CC1 DATAIN 20 DATAIN 19 SUBST 18 CLKIN 17 CLKIN 16 V EE 15 VCC1 14 AV CC 13 C8 -5.2V 0.1F R 80.6 C12 0.1F R34 130 R35 130 -5.2V -5.2V R17 80.6 R18 80.6 R1 100 R2 100 C3 0.1F C7 0.1F C10 0.1F R13 80.6 R14 80.6 3 4 R10 154 R5 100 R9 154 5 6 7 8 Z2 10H116 12 11 10 J6 9 DATAIN 16 15 14 13 R19 130 R20 130 J5 DATAIN -5.2V C11 0.1F
OBS
-5.2V 9 AVEE -5.2V C2 10F 10 ASUBST C6 0.1F
VCXO CONTROL 12 NC 11 R32 80.6 R33 80.6
Z1
AD805
R30 10k
C21 0.47F C20 0.47F
R28 10k
C10 0.1F 8
DIGITAL GROUND
ANALOG GROUND
NC = NO CONNECT
3 2
1/3 Z3
16
Figure 17. AD805-SAW Filter Clock Recovery and Data Retiming Circuit Schematic
Table II. AD805-SAW Filter Clock Recovery and Data Retiming Components List
OLE
R31 10k C19 0.47F R29 10k 1/3 Z3 1/3 Z3 10H116 C14 1nF R23 590 5 4 7 6 10 9 15 14 13 12 C15 1nF 1 R27 274 R26 274 R25 274 R24 274 -5.2V C17 0.1F -5.2V C16 0.1F
R22 590 TOYOCOM TQS-610J-6R
Reference Designator R1-R8 R9-R12 R13, R14, R17, R18, R32, R33 R15, R16, R19, R20, R34, R35 R21 R22, R23 R24-R27 R28-R31 C2 C3-C13, C16-C18 C14, C15 C19-C21 L1 Z1 Z2, Z3 Z4
Description Resistor, 100 , 1% Resistor, 154 , 1% Resistor, 80.6 , 1% Resistor, 130 , 1% Resistor, 226 , 1% Resistor, 590 , 1% Resistor, 274 , 1% Resistor, 10 k, 1% 10 F, Tantalum 0.1 F, Ceramic Chip 1 nF 0.47 mF 1 h, T50-10 Core, 18 Turns, Micrometals, Inc. AD805 1OH116, ECL Line Receiver Toyocom TQS-610J-6R SAW
Quantity 8 4 6 6 1 2 4 4 1 14 2 3 1 1 2 1
TE
L1 1h T50-10 CORE, 18 TURNS -5.2V C13 0.1F
R21 226
-10-
REV. 0
AD805
LARGE FACTOR FREQUENCY MULTIPLICATION -- TO 155.52 MHZ DESKEWING ISOCHRONOUS 155.52 MBPS DATA STREAMS
OBS
60 50 OUTPUT JITTER - ps rms 40 30
The AD805-VCXO combination can be used to multiply a frequency at the AD805's DATAIN by a large integer multiple. This is useful for generating a 155.52 MHz bit clock from a 19.44 MHz byte clock (multiplication factor of 8). The highly accurate center frequency of the VCXO makes even larger factor frequency multiplication possible. The VCXO will not lock on a false harmonic even for large multiplication factors. For example, a VCXO with center frequency accuracy of 100 ppm will allow frequency multiplication by a factor as large as 5000. This is because the 5000th harmonic of 31.104 kHz is 155.52 MHz, and the 4999th and the 5001st harmonics are 200 ppm away from the VCXO center frequency. Since the accuracy and tuning range of the VCXO constrain its output frequency to within 100 ppm of center frequency, the circuit will reliably pick the 5000th harmonic. Frequency multiplication by an odd factor is possible using the AD805-VCXO combination. This is not obvious. Consider a 51.84 MHz input multiplied by a factor of 3 to get to 155.52 MHz. In this case, the edge spacing of the 51.84 MHz signal is 9.65 ns, or 1-1/2 periods of the expected 155.52 MHz output. In theory, every other edge of the 51.84 MHz at the AD805's DATAIN is interpreted as 180 out of phase. In practice, however, the inherent loop jitter dithers these edges to give +179 then -179 out of phase measurements on alternate edges. Measurements on these alternate edges cancel. The circuit phase locks to the other set of alternate edges. The very low gain of the VCXO and the narrow bandwidth of the jitter transfer function gives an output that has low jitter even though alternate input edges are out of phase. When multiplying by a factor of 3, the DATAOUT will have a repeating 110 or 100 pattern. Either pattern can occur since either the rising or falling edges of the 51.84 MHz signal at the DATAIN can be the out of phase set of alternate edges. Figure 18 shows the output jitter performance of an AD805VCXO circuit for different integer frequency multiplication factors.
The AD805 can be used for deskewing a 155.52 Mbps data stream to a reference 155.52 MHz clock when the clock is isochronous with the data. Figure 19 shows a diagram of an AD805 in a deskewing application. The data input to the AD802-155 clock recovery circuit and the data input to the AD805 were generated using the same 155.52 MHz clock. The AD805 data retiming loop formed by the voltage-controlled phase shifter, the phase detector, and the loop filter act to align the phase of the input data to the phase of the recovered clock. This eliminates skew that can exist between two isochronous data paths. The AD805 will track 180 change in skew after initial locking without bit errors. If the skew changes by more than 180 after lock, it is possible to exceed the range of the voltage controlled phase shifter. Exceeding the phase shifter range will force the AD805 data retiming loop to reacquire to the center of the phase shifter. During this reacquisition, it is possible to make 3000 bit errors.
CD
OLE
REFERENCE DATA INPUT PHASE DETECTOR FREQUENCY DETECTOR
COMPENSATING ZERO
RETIMING MODULE
AD802-155
TE
LOOP FILTER VCO LOOP FILTER GAIN
RECOVERED CLOCK
RETIMED DATA FRAC OUTPUT
DATA INPUT
VOLTAGE CONTROLLED PHASE SHIFTER
PHASE DETECTOR
VCXO CONTROL OUTPUT
RETIMING MODULE BUFFERED CLOCK
AD805
RETIMED DATA
Figure 19. AD805 Deskewing Circuit Diagram
20
10
0 10 INPUT CLOCK FREQUENCY - MHz 100
Figure 19. AD805-VCXO Circuit Clock Output Jitter vs. Integer Multiplier
REV. 0
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AD805
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic Dual In-Line Package (N-20)
C1777-10-4/93
1.060 (26.90) 0.925 (23.50)
20 1 11 10
0.280 (7.11) 0.240 (6.10)
PIN 1 0.210 (5.33) MAX
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.100 (2.54) BSC 0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
OBS
0.160 (4.06) 0.115 (2.93)
0.022 (0.558) 0.014 (0.356)
0.015 (0.381) 0.008 (0.204)
OLE
TE
PRINTED IN U.S.A.
-12-
REV. 0

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